The companies will develop virtual models, simulation and lithography techniques to address fabrication challenges and prepare the architecture for production.
IBM announced new research aimed at advancing IBM’s nanostack architecture, a new transistor architecture unveiled by IBM earlier this year. The collaboration will bring together IBM’s leadership in semiconductor device innovation and Siemens’ expertise in electronic design automation (EDA), process simulation, lithography optimization, and advanced manufacturing software to accelerate the development of nanostack.
Nanostack is the industry’s first known three-dimensional, nanosheet-based design, vertically stacking and staggering transistors to pack more transistors onto a chip, with nearly 100 billion transistors in a space the size of a fingernail at its current 7 angstrom node. The design also unlocks the use of different material combinations within each stacked layer to optimize performance and power efficiency of each transistor independent of the other. These innovations power substantial leaps in energy efficiency, performance, and SRAM scaling.
Earlier this year, IBM demonstrated the viability of the nanostack architecture. Now, additional advances are needed to prepare the technology for manufacturing and production at scale.
Through this collaboration, IBM and Siemens will work to advance the design, simulation, and lithography techniques needed for this and future nanostack generations beyond the current 7 angstrom node. The collaboration includes developing advanced virtual models of nanostack in order to model performance, optimize designs, and address fabrication challenges before chips are built.
By combining IBM’s semiconductor leadership with Siemens’ advanced EDA software and simulation technologies, the companies aim to accelerate technology development cycles and advance the manufacturing foundation necessary for bringing nanostack toward production.
For more information, visit ibm.com.
