Successful customer tape out of HBM3 design on SF2 process and I-CubeS technology leveraged Synopsys 3DIC Compiler to reduce turnaround time by 10X.
Synopsys, Inc. announced its ongoing close collaboration with Samsung Foundry to power the next generation of designs for advanced edge AI, HPC, and AI applications. The collaboration between the companies is helping mutual customers achieve successful tape-outs of their complex designs using Synopsys’ 3DIC Compiler and Samsung’s advanced packaging technologies with fast turnaround time. Mutual customers can improve power, performance and area (PPA) with certified EDA flows for SF2P process, and minimize IP integration risk with the high-quality portfolio of IP on Samsung’s most advanced process technologies.
Successful Collaboration on Multi Die Design
Synopsys and Samsung are powering the most complex multi-die designs to enable mutual customers to rapidly deliver advanced technologies to the market. The companies’ most recent collaboration includes a successful tape-out of a customer design using Synopsys’ 3DIC Compiler, a unified exploration-to-signoff platform, and Samsung’s I-CubeS 2.5D packaging technology, which allows several HBM stacked dies on a silicon interposer. In addition to substantially reducing HBM routing time to 4 hours, the Synopsys 3DIC Compiler improved worst-case eye opening by 6% for better performance and reliability. The ongoing projects leverage 3DIC Compiler’s rapid 3D floorplanning with bump and Through-silicon via (TSV) planning and early thermal analysis, which is certified by Samsung for Samsung’s X-Cube technology.
Collaboration on Design Technology Co-Optimization and EDA Flows
Synopsys and Samsung Foundry have had a decades-long collaboration using AI-driven design technology co-optimization (DTCO) to achieve superior PPA entitlement on SF2 and SF2P processes. Synopsys and Samsung also continue to collaborate on AI-driven flows using Synopsys ASO.ai, resulting in a new schematic migration flow to efficiently migrate Samsung SF4 analog IPs to the SF2 process.
In addition, Synopsys’ AI-driven digital and analog flows have achieved certification on Samsung Foundry’s SF2P process with hypercells enablement for more efficient use of standard cell space, improving overall PPA, along with certified digital and analog flows for SF2/SF2P generation nodes. The flows, powered by the Synopsys.ai full-stack EDA suite, allow mutual customers to accelerate development of differentiated SoCs on Samsung’s advanced process technologies.
Broad Portfolio of Synopsys IP for Samsung Foundry Speeds Time to Market
Synopsys and Samsung Foundry continue a strategic relationship to provide chipmakers with a comprehensive portfolio of high-quality IP optimized for performance, power, area, and latency across Samsung’s advanced process nodes, from 14LPP/U, 8LPU, SF5A to the latest SF4X and SF2P/A. This collaboration supports a wide range of applications, including high-performance computing, consumer electronics, mobile devices, IoT, and automotive markets. Synopsys offers a broad portfolio of interface IP – such as and 224G, UCIe, PCIe 7.0, MIPI, LPDDR6X and USB4 – alongside foundation IP, including embedded memories, logic libraries, GPIOs, and PVT sensors, as well as security IP and Silicon Lifecycle Management (SLM) IP. By delivering trusted, low-risk solutions tailored to Samsung’s processes, Synopsys enables mutual customers to accelerate time-to-market and gain a competitive edge for their advanced designs.
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