You Need to See the Trends of Silicon Lifecycle Management

SLM utilizes PLM strategies to support the performance of electronics from cradle to grave.

The electrification trend is a boon for product sales and performance, but it introduced a Trojan horse into the market during silicon chip shortages. (Stock photo.)

The electrification trend is a boon for product sales and performance, but it introduced a Trojan horse into the market during silicon chip shortages. (Stock photo.) 

The 2020 chip shortage, instigated by the COVID-19 pandemic, made a major impact in the electronics market. The ripples have not only shaken the entertainment sector, they have also affected smart devices and current automotive models

The electrification boom has created positive outcomes like increased efficiency, automation, and connectivity opportunities. But it has also introduced an Achilles’ heel into the market: If all products rely on chips, then their success depends on the ability of the electronics industry to meet the demand and performance throughout the lifecycle of those products.

Product lifecycle management (PLM) solutions have paved the way to improve prices, optimize workflows, and maximize customer opinions of various products. The challenge is that the silicon chips used to control these products rarely undergo the same level of scrutiny. As the complexity and performance of these chips are expected to be higher, this all puts a bigger strain on their reliability, maintenance and optimization. In short, the more the electrification trend grows, the bigger the market risk during silicon chip shortages.

In response, various electronic design automation (EDA) organizations have started shifting attention toward a lifecycle approach. Thanks to a new process called silicon lifecycle management (SLM), these companies can better understand how their electronics perform from cradle to grave. This will enable their customers to better plan and optimize their products throughout their life cycles. 

“We see three key trends to SLM,” said Aileen Ryan, senior director of Portfolio Strategy at Siemens Digital Industries Software. “The first is nodal scaling, as transistors get smaller, the potential for defects increase. The second is design scaling, or the increasing complexity of individual chip designs. And then there is system scaling, which is the number of chips within a device. The reliance on electronics—including the electrification and automation of various markets—is driving us to support our customers’ chips throughout their entire lifecycle.”

What Is Silicon Lifecycle Management (SLM) and How Does It Work?

SLM data can improve chip design, manufacturing, testing, product integration, testing, deployment and operations. (Image courtesy of TechPerSpec.)

SLM data can improve chip design, manufacturing, testing, product integration, testing, deployment and operations. (Image courtesy of TechPerSpec.)

The core step behind the SLM process—and one that has rarely been done before—is the continuous collection of physical and functional data from noninvasive sensors that live directly on the chips themselves. 

Traditionally, these tests were only performed at certain times as the testing itself would affect chip performance. But, by collecting this data noninvasively and continuously, engineers can perform analytics to better understand how to optimize the silicon for each stage of its lifecycle, namely: design, manufacturing, testing, product integration, deployment and operations.

“There are two elements we are trying to achieve. One element is that the individual chip becomes self aware—improving resiliency, uptime, safety, and security. Our customers want to ensure that chips are behaving as expected throughout their entire lifetime,” said Ryan.

She added, “The second aspect is that data should be collected from a whole population of chips in the field. If I am seeing a lot of early failures in the field, I can correlate it with other data to generate additional lifecycle value by predicting if other chips from that batch, and future batches, will fail. PLM offers not just cost reduction capabilities, but also additional value creation abilities. SLM provides a valuable source of data for PLM projects within various industries.”

As for what data is being collected, sources include:

  • Built-in self-test (BIST)
  • Design for Test (DFT) 
  • Process , voltage, temperature (PVT) sensors
  • Resource and functional monitors

Once the data is processed, the insights it produces can improve a chip’s speed, performance security, and life at each point of its lifecycle.

When and How Should SLM Be Used for Maximum Benefit?

Chips can use SLM data to adapt to conditions in real time. (Image courtesy of Intel.)

Chips can use SLM data to adapt to conditions in real time. (Image courtesy of Intel.) 

Since SLM is a lifecycle process, it not only helps the chip designers; it also helps product designers and end users. For instance, the data collected on the chip during its manufacturing could potentially be used to optimize:

  • The chip’s design 
  • Alignment between virtual and physical models
  • Root cause analyses
  • Tolerance
  • Yield

As the chips move through their lifecycle, and data is collected and processed, engineers can expand the improvements they make. For instance, they can correlate the data on the chip during manufacturing to quality assurance (QA) data. They can then add alerts to the manufacturing process that predicts QA failures based on the data collected on the chips during manufacturing. A similar workflow can then be performed by the engineers who manufacture products that use the chips.

As for the operation stage, SLM data can be compared to how communication, computation and storage performance changes as the chip ages. Once the data is understood, engineers can set up systems that can predict failures and optimize chip performance and life based on the data gathered from the chips in operation.

This can go a step further, with analysis of the chip’s performance being compared to the chip’s environment, system, workload, security breaches and operating parameters. As the engineers learn more, they will be better able to improve the chip’s lifecycle.

According to Ryan, “the data isn’t just for post processing analytics, it can also be used by the chip itself. The chip can assess its own performance, and its environment, to understand and adapt to conditions in real-time.” 

Who Are the SLM Players?

In June 2020, Siemens made a big SLM play by acquiring UltraSoC. This expands the company’s Xcelerator portfolio and Mentor’s Tessent software to include SLM capabilities. With UltraSoC, Siemens has access to instrumentation and analytics solutions that can monitor the chips and perform analytics on their data.

Tessent Silicon Lifecycle Solutions diagram. (Image courtesy of Siemens.)

Tessent Silicon Lifecycle Solutions diagram. (Image courtesy of Siemens.)

Siemens’ aim is to help engineers improve product quality, safety and cybersecurity by using SLM tactics to discover manufacturing defects, software/hardware bugs, and the early-failure and wear-out of products. 

 “By utilizing design augmentation to detect, mitigate and eliminate risks throughout the system-on-chip (SoC) lifecycle,” said Ryan, “customers can radically improve time-to-revenue, product quality, safety, and profitability.”

The Siemens EDA Silicon Lifecycle Solutions portfolio includes:

  • Tessent Test Solutions for structural monitors
  • Tessent Embedded Analytics for functional monitors that observe the interactions between the chip, subsystems and embedded software
  • Tessent Diagnosis, YieldInsight and SiliconInsight for diagnostic-driven yield analysis flow, systematic yield limiters identification, debug and characterization 
  • Tessent SystemInsight for abnormal behavior identification (when software and firmware are loaded onto the chip)

Synopsys is a big player in the SLM world. Its Synopsys SLM Platform includes:

  • Monitoring and sensor intellectual property (IP)
  • TestMAX and Fusion Compiler to integrate the sensors and monitors onto chips
  • PrimeShield to minimize required margins and optimize power, performance and area (PPA), reliability and silicon predictability
  • Yield Explorer and SiliconDash to assess manufacturing, testing and operational efficiencies
  • TestMAX ALE and TestMAX SLT for die testing and in-system tests

In November of 2020, Synopsys also acquired Moortec, which will enrich its ability to produce in-chip monitoring technology such as PVT sensors. These sensors will provide real-time, on-chip data that can be fed into analytics systems.

Sassine Ghazi, chief operating officer of Synopsys said, “This acquisition accelerates the expansion of our SLM platform by providing our customers with a comprehensive data-analytics-driven solution for devices at the most advanced process nodes.”

ProteanTecs, a collaborator of Siemens and another SLM player, was founded in 2017. ProteanTecs advertizes the ability to embed agents onto chip designs that can pass data to its software platform to: 

  • Detect outliers
  • Predict maintenance
  • Improve yield
  • Speed up product introduction
  • Perform post- to pre-correlations
  • Tune performance
  • Reduce time to resolution
  • Produce high resolution binning

Though not an SLM solution, Cadence also offers technology that can interface with enterprise PLM. So, it wouldn’t be surprising to see the company become a SLM player in the future. 

Written by

Shawn Wasserman

For over 10 years, Shawn Wasserman has informed, inspired and engaged the engineering community through online content. As a senior writer at WTWH media, he produces branded content to help engineers streamline their operations via new tools, technologies and software. While a senior editor at, Shawn wrote stories about CAE, simulation, PLM, CAD, IoT, AI and more. During his time as the blog manager at Ansys, Shawn produced content featuring stories, tips, tricks and interesting use cases for CAE technologies. Shawn holds a master’s degree in Bioengineering from the University of Guelph and an undergraduate degree in Chemical Engineering from the University of Waterloo.