Superconducting Microprocessors Use 80 Times Less Energy Than Semiconductor Counterparts

New microprocessor prototype seeks to achieve up to 10GHz clock speeds.

A team of researchers from Yokohama National University in Japan has developed the world’s first adiabatic superconducting microprocessor, suggesting the possibility of computation 80 times more efficient than conventional microprocessors.  

The new microprocessor prototype, Monolithic Adiabatic iNtegration Architecture (MANA), is built with more than 20,000 Josephson Junction (JJ) switches made with niobium. The JJ switches are organized into logical primitives called adiabatic quantum-flux-parametrons (AQFPs).

The MANA is the first adiabatic superconducting microprocessor. (Image courtesy of Christopher Ayala/Yokohama National University.)

The MANA is the first adiabatic superconducting microprocessor. (Image courtesy of Christopher Ayala/Yokohama National University.)

This breakthrough in microprocessor technology not only promises more efficient computing but also more powerful computing.

“The AQFPs used to build the microprocessor have been optimized to operate adiabatically such that the energy drawn from the power supply can be recovered under relatively low clock frequencies up to around 10 GHz”, said Christopher Ayala, associate professor at the Institute of Advanced Sciences at Yokohama National University and one of the researchers who worked on bringing the AQFP MANA processor to life. “This is low compared to the hundreds of gigahertz typically found in conventional superconductor electronics.”

However, the current generation of the MANA microprocessor doesn’t yet achieve 10GHz speeds. The team demonstrated clock speeds up to 2.5 GHz, in the vicinity of semiconductor computing, but Ayala claims that he and his team “expect this to increase to 5-10 GHz as we make improvements in our design methodology and our experimental setup.” 

1.The logic schematic and clocking scheme of the adiabatic-quantum-flux-parametrons.  The physical layout of the AQFPs. Gates are arranged in logic rows where each row is clocked by one phase of the power-clock. Data propagate from one row to the next row, phase by phase. (Source: IEEE Journal of Solid State Circuitry)

(A) The logic schematic and clocking scheme of the adiabatic-quantum-flux-parametrons. (B) The physical layout of the AQFPs. Gates are arranged in logic rows where each row is clocked by one phase of the power-clock. Data propagate from one row to the next row, phase by phase. (Source: IEEE Journal of Solid State Circuitry)

It is estimated that data centers currently consume about 2 percent of all generated electricity, and that figure is on pace to reach nearly 10 percent by 2030. This poses not only efficiency concerns but also sustainability concerns since that electricity needs to be generated and the carbon footprint must be accounted for.

Although the MANA technology is still in the early stages, it shows potential for increasing computing efficiency and reducing the overall amount of energy required for computing.