Si, SiC, and GaN for Power Devices, Part Three: GaN Cascode FETs and E-HMETs

The third part of our series contrasting power devices of silicon, silicon carbide, and gallium nitride.

Which semiconductor is the power powerhouse? In this four-part series, we’ll take an in-depth look at the differences between silicon (Si), silicon carbide (SiC), and gallium nitride (GaN) to understand which is best for power devices and why.

In part one, we reviewed electron energy and semiconductors.

In part two, we looked at legacy silicon devices like the IGBT and the power MOSFET.

In part three, we’ll examine and contrast GaN cascode FETs with GaN Enhancement High Mobility Electron Transistors (E-HMETs).

The biggest advantages of GaN are providing better high frequency and high voltage performances. This results in developing power device designs that are smaller in size and at a reduced cost. GaN offers characteristics that exceed those possessed by SiC in all major respects, except SiC has a higher thermal conductivity and melting point than GaN. This means SiC is better at operating at higher temperatures than GaN.

As we shall see, there are two major approaches to producing GaN power devices: the cascode arrangement and Gallium Nitride Enhancement High Electron Mobility Transistors (GaN E-HEMT). Both designs are in use currently. The cascode arrangement will be discussed first.

The word “cascode” was derived from “cascade to cathode”. This goes back to the era of vacuum tubes (see Figure 19(a)). This cascode arrangement provided several advantages over the single stage amplifier such as better input output isolation, increased gain, greater bandwidth, and higher input impedance.

Figure 19(b) identifies the (control) grid, anode (plate), the cathode, and the heater (filament). The cascode arrangement employs a common cathode circuit that drives a common grid amplifier (Figure 19(c)). The MOSFET equivalent is shown in Figure 19(d).

Figure 19. Cascode arrangement.

When we examine the physical and electrical nature of GaN HEMT devices, there is one obvious challenge. A GaN HEMT’s natural operation mode is as a depletion mode FET with a natural “ON” state. The V-I transfer characteristic curve of a depletion-mode FET is shown in Figure 20. At issue here is the fact that with a v_GS of 0 V, the device will pass maximum current. The device is categorized as being “normally ON”. In power applications this is not acceptable. Negative values of v_GS are required to reduce the drain current.

Figure 20. Depletion-mode FET.

The stacked die cascode packaged device consists of a normally OFF low-voltage, low R_DS(ON) silicon MOSFET that is placed in series with the normally ON GaN HEMT device. The equivalent circuit of the cascode device is provided in Figure 21.

Figure 21. GaN Cascode device. (Image courtesy of Nexperia.)

The device gate is connected to the gate of the common-source input MOSFET. The input MOSFET is constructed from either Si or SiC. The gate of the silicon device can tolerate voltages beyond the capabilities of the GaN depletion-mode FET. The (normally ON) depletion FET is held OFF by the non-conducting SiC MOSFET in series. Consequently, the combination behaves like a normally-OFF device.

The cascode GaN FET has an effective gate rating of ± 20 V (equal to existing silicon super junction technology) and can be driven by standard cost-effective gate drivers with a simple
0 to 10 V or 0 to 12 V drive voltage. Yet it maintains the improved voltage blocking characteristics and switching performance of a normally ON GaN HEMT.

The rise and fall times can be adjusted with resistors in series with the output of the driver. This is sometimes described as making the GaN device “tunable”. Having a tunable low-voltage MOSFET in series does increase the R_DS(ON) and Q_RR (reverse recovery charge) of a cascode-mode device. However, these increases are often minimal when contrasted against the benefits that a robust and reliable insulated (dielectric) gate structure and high-performance body diode bring to GaN HEMT operation.

Toshiba announced an improved cascode device on September 30, 2020. The new device is shown in Figure 22.

Figure 22. Improved GaN cascode device. (Image courtesy of Toshiba.)

Toshiba’s new GaN cascode FET is claimed to be less susceptible to noise, often a source of malfunction, as it has a higher threshold voltage than the p-GaN gate found in normally-OFF HEMT devices. According to Toshiba, it also does not require designated driver integrated circuits.

It is normally difficult for this type of cascode configuration to control its switching speed via an external gate resistor. This is because it uses a silicon MOSFET to drive the GaN HEMT. Toshiba solved this by developing a device with direct gate drive, where driver ICs directly drive the GaN HEMT.

This supports changes to its switching speed, like silicon power devices, which helps to simplify the overall design of power electronics systems.

The new device contributes to stable operation. Specifically, false-ON due to voltage changes in the silicon MOSFET from an external source are minimized. This is because the GaN HEMT gate is controlled independently.

This structure eliminates the need to employ a cascode arrangement. The basic arrangement of a gallium nitride E-HEMT is given in Figure 23.

Figure 23. (Used with author’s permission from Discrete and Integrated Electronics Analysis and Design for Engineers and Engineering Technologists.)

Observe the device sports a heterojunction. A heterojunction is a special type of semiconductor junction that is formed between two different semiconductors. In this instance, “different” means two semiconductors with different energy bandgaps. Aluminum gallium nitride (AlGaN) is a semiconductor with a bandgap that can be tailored from 3.4 eV to 6.2 eV. Gallium nitride (GaN) has a bandgap of 3.4 eV. At the junction, a two-dimensional electron gas (2DEG) is produced. Since it only exists at the interface, it can be thought of as having no height. Hence, it can be viewed as a two-dimensional sheet in three-dimensional space. The electron density is large, and the electrons have high mobility.

Observe that we have three terminals: source, gate, and drain. When the gate-to-source voltage is less than the required threshold voltage, the channel in non-conducting, which means the drain current is zero. When the gate-to-source exceeds the threshold voltage, drain current will begin to flow. It follows the square law that occurs in a “regular” enhancement-only MOSFET. The biased condition is illustrated in Figure 24.

Figure 24. (Used with author’s permission from Discrete and Integrated Electronics Analysis and Design for Engineers and Engineering Technologists.)

Figure 25 illustrates the V-I drain characteristic curves for a GaN E-HEMT.

Figure 25. (Used with author’s permission from Discrete and Integrated Electronics Analysis and Design for Engineers and Engineering Technologists.)

Two of the huge advantages of using GaN devices is the improved performance at high frequencies and at high voltages. The frequency and voltage capabilities result in power devices that are smaller in size and at reduced cost. High-frequency capability requires careful printed circuit board design including power and ground planes to minimize inductance. The gate-drive signals often require tailored attention. Examine Figure 26.

Figure 26. Minimizing inductance using devices that incorporate GaNPX Packaging. (Image courtesy of GaN Systems.)

The elements incorporated in the GaNPX package by GaN Systems are indicated in Figure 27.

Figure 27. Elements of GaNPX packaging. Key below. (Image courtesy of GaN Systems.)

The following keyed comments are to be applied to Figure 27:

1. The GaN on Si die is mechanically mounted to the copper base plate.
2. High-temperature fiber glass sheets (with rectangular cutouts) are fit over the die.
3. Copper sheet is patterned and using a laser, vias to the die and through-hole vias to the bottom plate are created.
4. Copper plating is used to fill the vias.
5. The solder mask and product marking are applied.

The performance features of the GaN System GaNPX package are highlighted in Figure 28.

Figure 28. Features of the GaNPX packaging. (Image courtesy of GaN Systems.)

The animated process steps may be viewed using the (no-sound) video below:

GaN and Topologies

GaN offers the opportunity to create new topologies and enhance existing ones, which in many cases allows the reduction of component counts. This produces an increase in reliability. The bridgeless totem pole topology is now easily enabled with GaN Systems devices. GaN devices have no parasitic BJT or body diode and offer zero reverse recovery charge (Q_rr). Consequently, designers can implement topologies that take advantage of these characteristics. One of the efficiency limitations for AC offline applications has been the input bridge rectifier. By implementing the bridgeless totem pole architecture, the input bridge rectifier can be eliminated, and stages can be combined.

In other words, if rectification from the mains can be combined with the PFC (Power Factor Correction) function, then several benefits occur. There is an increase in the overall power converter efficiency by eliminating the forward voltage drop of the bridge rectifier. The GaN FET has no body diode, and this results in zero reverse recovery charge. The GaN FET can operate in the third quadrant. It is reverse conduction capable without the need for an anti-parallel diode. Hence, the external parts count is reduced.

Figure 29. E-HEMT in first and third quadrants. (Image courtesy of GaN Systems.)

In condition A v_GS is positive, as is v_DS. Condition B has v_GS positive and the drain current reversed, which is no problem for an E-HEMT or a MOSFET. C has the E-HEMT OFF and reversed drain current flowing through the device. This condition occurs when we have a synchronous buck inverter and both devices are non-conducting during dead time.

GaN Reduces Losses, Increases Efficiency, and Reduces Size

GaN reduces losses, increases efficiency, and reduces size (as less heat sinking is required and the size of magnetics components decreases). In DC-DC designs, especially in the ZVS (Zero Volt Switched) LLC converter, GaN technology contributes reduced output capacitance, C_OSS, which makes the converter not only easier to achieve ZVS, but also reduces the transformer losses and RMS currents. This translates to smaller magnetics resulting in higher efficiency typically by 50 to 90 percent, smaller size (a quarter of the original size in many cases), and higher power density. Consequently, there is an attendant weight reduction.

Figure 31. GaN reduces product size and weight. (Image courtesy of GaN Systems.)

Review and Conclusions

Gallium nitride (GaN) prevails in all major physical respects, except SiC has a higher thermal conductivity and melting point. There are two major implementations of GaN power devices: the cascode arrangement and the Enhancement High Electron Mobility Transistors (E-HEMT). The term “cascode” goes all the way back to the ancient days when vacuum tubes reigned supreme. The term is a contraction that refers to “cascade to cathode”. In the case of GaN power devices, it is a way to modify a normally-ON GaN device by using a silicon MOSFET in series to produce a combination that behaves like an enhancement FET.

The E-HEMT devices incorporate a heterojunction of aluminum gallium nitride (AlGaN) semiconductor next to gallium nitride (GaN). A heterojunction results when semiconductors with different bandgaps are placed together. At the junction, a two-dimensional electron gas (2DEG) is produced. The gate-to-source voltage controls the drain current and follows a square-law relationship.

Since the E-HEMT devices perform well at high frequencies, careful attention must be used in the design of printed circuit boards. Power and ground planes are noted for possessing low inductance. Layout is critical. However, the device packaging is also a major consideration. GaN Systems has a very low-inductance package for its GaN power devices.

GaN capabilities foster unique and innovative design approaches. Their efficiency requires less heatsinking with an attendant reduction in both size and weight—exactly what is prescribed for portable and aerospace applications.

In our fourth and final installment, we chat with the Chief Technology Officer at FTEX, a Canadian startup that focuses on the drive and control of light-weight electrical vehicles using GaN technology.