Supports UCIe 2.0 and OCP BoW standards for greater design flexibility.
Keysight Technologies, Inc. announced a collaboration with Intel Foundry to support Embedded Multi-die Interconnect Bridge-T (EMIB-T) technology, which is intended to enhance packaging solutions for AI, data center applications, and the Intel 18A process node.
As AI and data center workloads become more complex, reliable communication between chiplets and 3DICs is increasingly important. High-speed data transfer and efficient power delivery are key to meeting the needs of next-generation semiconductor applications. The industry is addressing these challenges with open standards like Universal Chiplet Interconnect Express (UCIe) and Bunch of Wires (BoW), which define interconnect protocols for integrating chiplets and 3DICs across various 2.5D/3D and laminate/organic packages.
By adopting these standards and verifying chiplets for compliance and link margin, Keysight EDA and Intel Foundry contribute to a growing chiplet interoperability ecosystem. The collaboration aims to reduce development costs, mitigate risk, and accelerate innovation in semiconductor design.
Keysight EDA’s Chiplet PHY Designer, the latest solution for high-speed digital chiplet design tailored to AI and data center applications, now offers advanced simulation capabilities for the UCIe 2.0 standard and introduces support for the Open Computer Project BoW standard. As an advanced, system-level chiplet design and die-to-die (D2D) design solution, Chiplet PHY Designer enables pre-silicon level validation, streamlining the path to tapeout.
For more information, visit keysight.com.
