***Security Requirements:

All applicants selected for this position will be required to obtain and maintain a US government security clearance.

***Relocation Package Available

***Pay Range (DOE):

$165,000K to $200,000K Plus Top benefits & 10% 410K

As a Principal CAD Engineer, you will be working with the design team in developing and implementing design flows for both analog and digital ASIC design from architecture to tape-out. You will be developing new design capabilities, testing and validating flows and running and debugging tools for every aspect of the design process.

Job Description:

• Client is seeking talented and motivated individuals to tackle challenging engineering problems in advanced digital IC design.
• As a Principal CAD Engineer, you will be working with the design team in developing and implementing design flows for both analog and digital ASIC design from architecture to tape-out.
• You will be developing new design capabilities, testing and validating flows and running and debugging tools for every aspect of the design process.
• You must have demonstrated prior experience developing scripts and flows with commercial EDA tools.
• The ability to manage Linux environments is also required.
• You must have the ability to proactively identify improvements to processes, implement them and roll them out to the team.
• Client develops novel digital, analog and mixed-signal ICs!

Required Qualifications:

• MSEE and 10+ years relevant experience designing, developing and supporting CAD tool flows for both analog and digital ASIC design.
• Ability to work with internal and external tool developers to implement enhancements to support a highly efficient work flow.
• Fluency in scripting languages and ability to develop tools Clear communication and ability to work well in teams.
• Familiarity with analog, digital and mixed-signal design flows Strong analysis and problem-solving skills.
• Experience with Linux/UNIX OS, patching, piping, batching, etc.

Preferred Qualifications:

• MS/PhD preferred.
• Experience with Cadence tool flows preferred.
• Fluent in VHDL and Verilog.
• Knowledge of SystemVerilog.
• Ability to provision new computer systems for ASIC design.