Senior Design Verification Engineer

Company Info
Capgemini Engineering
CA, United States

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Senior Design Verification Engineer


Menlo Park, CA 

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Job Description:

Capgemini Engineering combines, under one brand, a unique set of strengths from across the Capgemini Group: the world-leading engineering and R&D services of Altran – acquired by Capgemini in 2020 – and Capgemini’s digital manufacturing expertise. With broad industry knowledge and cutting-edge technologies in digital and software, Capgemini Engineering supports the convergence of the physical and digital worlds. Combined with the capabilities of the rest of the Group, it helps clients to accelerate their journey towards Intelligent Industry. Capgemini Engineering has more than 52,000 engineer and scientist team members in over 30 countries across sectors including aeronautics, automotive, railways, communications, energy, life sciences, semiconductors, software & internet, space & defense, and consumer products.

Design Verification Engineer

Full Time Role


  • Architect and Create verification environments using System-Verilog and Universal verification methodology-UVM IPs and SoCs with embedded CPUs and analog mixed-signal interfaces.
  • Develop test plans and coverage metrics from specifications and writing block and chip-level tests.
  • Create PERL/Python scripts to automate creating verification environments, tests generation and debugging.
  • Failure analysis of Register Transfer Level and Gate simulations and resolve them by working with design engineers.
  • Create low power testcases using UPF or CPF to verify the desired power intent of the SoC.
  • Work with architects to determine the use-case scenarios to simulate

Preferred Qualifications:

  • Proficiency in C-shell scripting, Verilog-HDL & System Verilog.
  • Strong knowledge in SV Assertions, UVM and functional code coverage.
  • SOC Verification experience using ARM Cortex Microcontroller is required.
  • Experience with advanced peripheral bus Verification IP’s such as GPIO, UART, SPI, SW, JTAG, and I2C.
  • Proficient with Cadence tools such as NCVerilog, NCSIM, Simvision. Experience with linting tools (i.e Spyglass) will be helpful.
  • Exposure to SDF annotated simulations with good understanding of parasitic delays and timings is required.
  • Independent, self-motivated with good analytical & communication skills.

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This company is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or veteran status