Looking for a Physical Design Engineer to work for an innovative company. This is a full-time opening with our direct client a leader in Semi-conductors’ industry

Requirements/Responsibilities

• 5+ years of professional experience
• Experience with ASIC Physical Design
• Experience hands-on with implementation EDA tools like ICC2/Innovus
• Experience with scripting (Perl/Tcl/Python)
• Expereince with ASIC Physical Design
• Experience with Physical Verification and fix PV errors in layout
• Expereince with both Flat and Hierarchical layouts
• Experience to articulate technical discussions with ASIC Customers and design teams
• Experience with power analysis and IR-drop tools (primepower/Redhawk) and Static Timing Analysis (Primetime)
• Experience with handling of Verilog HDL based Netlists, Physical design libraries
• Will work to analyze and resolve physical design issues related to library, timing constraints or CAD tools is required
• Will work on pre-layout STA to ascertain feasibility, timing constraint validation and feedback to customers and design teams
• Will work on Chip/Block Level Floor planning and pin assignment
• Will work to perform sign-off tasks (RC Extraction, Static Timing Analysis, IR drop analysis and Physical Verification)
• Will work to handle all the Physical design tasks (Placement, Timing Optimization, Clock Tree Synthesis, Routing)
• Will work to review top-level/block-level clock specifications for completeness and feasibility