Digging into Cadence’s new chip design tools for electronics engineers.
Electronics engineers and designers have a lot going on. Designs are becoming more complex, and their footprints are becoming smaller. Meanwhile, consumers want everything to happen faster with error-free designs, products and infrastructure. Electronics design can require several teams to work on different blocks of the same chip, and the interaction of these separate blocks causes headaches and adds extra time to the development process.
To combat this, Cadence recently launched its Certus Closure Solution, a productivity tool designed to pull time out of the chip development process. The San Jose, California simulation company was founded in 1988 and is a supplier of simulation tools that help electronics designers bring better products to market. Cadence pinpointed chip-level signoff and power, performance, area (PPA) requirements as two of the larger bottlenecks in the electronics design process. The company says that the Certus Closure tool can do this work for its customers in a tenth of the time that was previously required.
Dr. Chin-Chi Teng, Cadence senior vice president, said, “We are intensely in tune with the needs of the design community, and with the release of the new Cadence Certus Closure Solution, we’re offering our customers a novel environment for chip-level optimization and signoff that delivers exceptional PPA results within a matter of hours. With this new Cadence solution, we’re empowering customers to achieve productivity goals and deliver products to market faster.”
How Does Certus Do Its Work Faster?
The premise behind the Cadence tool is that it does a full-chip optimization using automated parallel-path operations instead of waiting for each function to go off on its own and complete tasks. In a blog entitled, “Cadence Certus Closure Solution: Automated Full-Chip Optimization,” Paul McLellan from Cadence estimated that one iteration through the chip assembly, static timing analysis, power optimization and block loop operations sequence could take five to seven days. Several iterations are needed to find a design that can pass all the verification steps, and McLellan said that the full design sequence might take months.
Certus is now controlling several of the timing and verification programs together to automate the processes and find a verified solution faster. Customers can use Tempus ECO for optimization of individual block components and its static timing analysis (STA) at the overall system-on-a-chip (SoC) level. A side benefit of working on the individual pieces while also keeping an eye on the assembly is a power recovery system that can save up to five percent of power use on a full chip. Cadence’s OnCloud platform means that customers can use this tool to develop much denser and more complex products than before.
A SmartHub interface gives the customer a graphic user interface (GUI) that can track progress for the individual block designs and the overall system. A downstream benefit to this compacted locus of control is the Integrity 3D-IC tool. When Certus is looking at the fully assembled chip in addition to each of the blocks, there are opportunities to find optimal paths for inter-die paths across the blocks.
Does Certus Work with Other Tools?
Cadence is a big player in the simulation field with a deep list of products, but is known more as a specialty supplier focused on electronics design automation (EDA). The company’s tools are broken into groups such as digital design, signoff, verification and integrated circuit package design. Unlike some of the more familiar names in the simulation field, such as Altair and Ansys, Cadence has a niche and chooses to focus its efforts there—at least for now. The overarching goal of simulation remains consistent, finding better solutions for engineers on a smaller timescale with a better fidelity of results.
Several EDA software are good at developing plugins or import modules that can bring designs in from one tool to another, and then do the processing in a native space. Cadence has several import tools to bring in designs and a Connections Program that works with third-party suppliers to help meet customer needs.
As Certus works as a Cadence tool that optimizes other Cadence tools, it makes sense for customers that use several of these products already. Instead of waiting for four different disciplines to do their work and bring the results back to the group, these signoffs and closures can be automated to find iterative solutions more quickly. No one is going to be smarter about the different Cadence tools than its own engineers, and bringing them together under one rebranded banner that can automate the iterations is not necessarily earth-shattering—but it is a great use of AI to find better solutions more quickly.
What Does It All Mean?
Even the most electrical-averse engineer must see the value in electronics design these days. As an undergraduate mechanical engineering student, I always thought of us as warring factions, with machine design being the meat-and-potatoes of the engineering world and the electrical engineers doing the more mystifying work. We all had to learn Laplace transforms when studying differential equations, but the electrical students put them to practical use beyond one unit in control systems classes? Unbelievable. One of the constant occurrences for me in the last few decades has been technology predictions that turn out to be way off-base. I remember wisecracking when the iPad was announced: why would you need a smaller computer screen or a larger phone screen? But it didn’t take long to find utility in a larger screen for reading, apps and streaming video.
Ten years ago, the connectivity that is everywhere and in almost every product was a wild idea that felt more like science fiction than the near future. On a personal level, we want data on everything, and that data requires electronics. A smart water bottle might seem like futuristic overkill but being reminded that it’s 8:00 pm and you haven’t had any water yet today is valuable to someone distracted by a busy day.
Industrially, we already use thousands of chips to control the systems that allow us to drive, access the internet and turn on light switches. The need for integrated circuit chips is only going to grow as vehicles become electrified, communication networks become more sophisticated and electrical grids search for the best ways to efficiently transmit power.
There’s a counter-intuitive aspect of Certus monitoring all the block designs and integration designs at once. Conventional wisdom said that no single engineer or even engineering team could design everything—we needed to break up systems into blocks and let various teams be the experts on their own block. Now this approach says that one system can verify all the sub-functions and enhance the full assembly using machine learning. It will be interesting to watch over the next five years of technology predictions and paradigm shifts to see if the ten times productivity gains from Certus are fully realized.
