High-performance solution with lowest area and power available now for customer engagements.
Cadence has introduced a 12.8Gbps HBM4 memory IP solution designed to meet growing memory bandwidth requirements for next-generation AI training and high-performance computing (HPC) systems. The solution complies with the JEDEC JESD270-4 specification and offers twice the bandwidth of the previous HBM3E generation. Now available for customer engagements, the HBM4 PHY and controller IP deliver 12.8Gbps performance, with improved power efficiency per bit and area efficiency, along with a higher number of I/Os to support increased bandwidth.
The new Cadence HBM4 IP offers a PHY and a high-performance controller as a complete memory subsystem solution. The HBM4 PHY will be available as a drop-in hardened macro in the TSMC N3 and N2 technology nodes, while the HBM4 controller will be provided as a soft RTL macro. The 12.8Gbps data rate exceeds the available HBM4 DRAM device speeds by 60%—giving designers ample system margin, enabling support for potential speed improvements, and future-proofing their SoC products. The high-performance, low-latency architecture includes RAS and BIST features for fine-tuning memory subsystem performance in the field for optimal data center operations. The standard HBM4 IP offering includes support for all flavors of interposer design implementation options and lab software for rapid memory subsystem bring-up of customer SoCs.
Cadence’s HBM4 solution includes a comprehensive set of deliverables for faster integration of the IP to SoC design and post-silicon bring up. The deliverables include a reference interposer design validated at 12.8Gbps on a full-featured test chip consisting of an HBM4 controller, PHY, interposer, and HBM4 DRAM device. LabStation software with extensive features and test suites for rapid SoC post-silicon lab bring-up is provided for faster time to market.
Cadence’s HBM4 PHY and controller have been verified with Cadence’s Verification IP (VIP) for HBM4 to provide rapid IP and SoC verification closure. Cadence VIP for HBM4 includes a complete solution from IP to system-level verification with DFI VIP, HBM4 memory model, and System Performance Analyzer.
For more information, visit cadence.com.
