Siemens’ circuit verification platform is certified for use with TSMC’s forthcoming N3 and N4 nodes.
The recent Taiwan Semiconductor Manufacturing Company (TSMC) 2021 Online Technology Symposium was the setting for many developments in process technologies, including an announcement from Siemens Digital Industries Software that its Analog FastSPICE platform and Calibre nmPlatform tools are qualified for TSMC’s upcoming N3 and N4 processes. The announcement follows the development in early 2021 that Siemens’ Analog FastSPICE platform was certified for use with Samsung Foundry’s 3nm node.
“Siemens has consistently partnered with TSMC at the earliest stages of each new technology node, enabling the foundry to deliver out-of-the-box, high-performing and accurate decks for our mutual customers,” said the executive vice president for IC EDA at Siemens Digital Industries Software, Joe Sawicki. “Siemens is a proud, longtime partner with TSMC, and for our mutual customers this translates to state-of-the-art performance and power efficiency.”
Beyond Analog FastSPICE, several tools from the Siemens’ Calibre nmPlatform, including Calibre nmDRC software, Calibre PERC software, Calibre SmartFill, Calibre xACT, and Calibre nmLVS software, were certified for the forthcoming TSMC N3 process, and all except for Calibre xACT were also certified for TSMC N4.
Siemens’ Analog FastSPICE Platform
The Analog FastSPICE platform enables circuit verification to nanometer accuracy. Siemens designed the platform to meet the evolving needs of the semiconductor industry and processes that maximize performance, size and cost. The platform claims industry-leading verification for nanometer analog, radio frequency, mixed-signal, memory, and custom digital circuits.
According to Siemens, the Analog FastSPICE platform is more than five times faster than traditional SPICE platforms and three times faster than post-layout SPICE.
TSMC Next Generation Processes
At its first ever online symposium, TSMC showcased its forthcoming N4 and N3 processes. Compared to its N5 process, N4 will improve performance and efficiency while increasing the density of transistors. Risk production is now set for late 2021 and will occur in parallel with the continued development of the N3 process.
