EW – Design Edition – Cadence Verification Suite, Xilinx Heterogeneous Computing & More
Vincent Charbonneau posted on October 31, 2018 |

Altium Cloud Infrastructure for Manufacturing

Altium 365. (Image courtesy of Altium.)
Altium 365. (Image courtesy of Altium.)

Altium has announced a cloud infrastructure that facilitates better, more connected collaboration across design and product realization disciplines. Altium 365, a cloud-based platform, is the first step in directly connecting desktop printed circuit board (PCB) design with the manufacturing floor.

With availability targeted for December 2018, Altium 365 integrates with Altium Designer 19 and utilizes the power of the cloud to connect designers, component distributors and manufacturing stakeholders and make it easy to share information and design collaboratively.

For more information, visit Altium’s website.

Arm FPGA Option for DesignStart

Arm DesignStart platform. (Image courtesy of Arm.)
Arm DesignStart platform. (Image courtesy of Arm.)

Arm announced that its Cortex-M1 and Cortex-M3 cores have been added to the DesignStart portfolio in a collaboration with Xilinx to bring instant and license-free access to developers. Modifications made to the Cortex-M1 for DesignStart FPGA represent a change to the AXI interface that allows users to design with the Vivado environment and peripherals. Optimization in the pipeline to fit FPGA structures and changes to the memory interface structure make use of memory in FPGAs that are configured as tightly coupled memories (TCMs).

For more information, visit Arm’s website.

Cadence Verification Suite Enabled on Arm-Based HPC DataCenters

Cadence Verification Suite and HPC datacenter functionality. (Image courtesy of Cadence.)
Cadence Verification Suite and HPC datacenter functionality. (Image courtesy of Cadence.)

Cadence announced that its Verification Suite is now enabled for Arm-based high-performance computing (HPC) server environments. Through an industry ecosystem collaboration, software tools in the Verification Suite, including Xcelium Parallel Logic Simulation, run on the HPE Apollo 70 System, which is built using the Marvell Thunder X2 processor based on the Armv8-A architecture.

The joint venture provides users with a compute option that HPE indicates can be up to 19 percent more cost-effective than other HPE industry-standard servers, providing a level of flexibility to make trade-off decisions pertaining to internal project priorities, user license allocation, unlicensed task execution and time to project completion.

For more information, visit Cadence’s website.

Imagination Low-Power Wireless on SoCs

Ensigma Radio IP. (Image courtesy of Imagination Technologies.)
Ensigma Radio IP. (Image courtesy of Imagination Technologies.)

Imagination Technologies and Global Foundries have collaborated to provide low-power wireless baseband and RF functions—Bluetooth Low Energy and IEEE 802.15.4, for instance—to mutual users.

“22 FDX is an appealing option for customers designing cost-sensitive devices,” said Imagination Executive VP of Marketing David McBrien. “The collaboration has made our Ensigma connectivity IP even more power and area efficient. The availability of baseband and RF enables customers to introduce single-chip wireless devices requiring only a single external antenna.”

For more information, visit Imagination’s website.

Xilinx Heterogeneous Computing

Versal AI and Versal Prime. (Image courtesy of Xilinx.)
Versal AI and Versal Prime. (Image courtesy of Xilinx.)

Xilinx has introduced Versal AI and Versal Prime in response to the need for heterogeneous computing that can process the volumes of data in use today.The AI Core series is designed to blend inference with scalable engines for the adaptable workloads of the application. The series is optimized for cloud, networking and autonomous technology, and is made up of five devices with 128 to 400 AI Engines.

The devices are based on dual-core Arm Cortex-A72 application processors and dual-core Arm Cortex-R5 real-time processors. In addition to 1.9 million system logic cells, there are 32 megabits worth of Accelerator RAM blocks that support custom memory hierarchies.

For more information, visit Xilinx’s website.

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