DARPA’s $100 Million Programs for a Silicon Compiler and a New Open Hardware Ecosystem
Andrew Wheeler posted on July 05, 2018 |

Moore’s Law Is Slowing Down

Designing and manufacturing CPUs and GPUs for engineers means finding ways to reduce the size of transistors while ensuring scalability for mass production. The scale of transistors embedded on silicon chips has shrunk for many years according to Moore’s Law, which allowed information technology and electronics giants like Apple and Microsoft to produce reliable projections for increasing computational speed and complexity. The whole computing industry continues to be built on the basic idea that more transistors equals better performance. But Moore’s Law is running smack into the limits of manufacturing and the laws of physics.

This Extreme Ultraviolet Lithography tool at Lawrence Livermore National Laboratory coats super thin films on wafers to make integrated circuits that are completely defect-free. (Image courtesy of the U.S. Department of Energy.)
This Extreme Ultraviolet Lithography tool at Lawrence Livermore National Laboratory coats super thin films on wafers to make integrated circuits that are completely defect-free. (Image courtesy of the U.S. Department of Energy.)

Photolithography is the method by which transistors are carved out of silicon wafers using beams of light. Since the goal of this process is perpetual miniaturization of transistors, the level of detail is directly proportional to the wavelength of light used. Until now, engineers have relied on photolithography processes that use shorter and shorter wavelengths of light to etch smaller and smaller transistors. But since the energy available in light is inversely proportional to the wavelength, shorter and shorter wavelengths use more energy and the process becomes increasingly unwieldy.

So, why is Defense Advanced Research Projects Agency (DARPA) spending $100 million on an initiative to reduce the complexity of designing silicon chips?

The simple answer is that the cost of designing a hyper-advanced system-on-a-chip (SoC) is approaching $500 million. This is incredibly expensive. After shrinking transistors powered five decades of advances in computing, there may only be a few years left of predictable transistor shrinkage. Chip manufacturers are looking for new and innovative ways to keep Moore’s Law going.

DARPA’s IDEA and POSH Programs

Intelligent Design of Electronic Assets (IDEA) and Posh Open Source Hardware (POSH) are the names of two research programs slated to receive $100 million in funding over the next four years, with the goal of creating a software system similar to silicon compilers that can lower the complexity currently required by engineers to design faster chips.

Though the definition of a silicon compiler has changed alongside advances in CAD software, it is basically a system of software that converts user-input specifications into an integrated circuit (IC). A silicon compiler translates electronic designs of chips into layouts of logic gates, which include the masking of one transistor to another.

These two research programs run by DARPA are just a small part of a $1.5 billion Electronics Resurgence Initiative (ERI) designed to boost the electronics industry in the United States. POSH and IDEA work hand in hand in the following way: The goal of POSH is to create an open-source library of silicon blocks and the purpose of IDEA is to create an array of open-source and enterprise tools to automate testing of those blocks and weave them into SoCs and printed circuit boards.

Bottom Line

The goal is to infuse some of the open software movement into hardware, giving companies the ability to design low-volume chips that would otherwise be cost-prohibitive. The idea is that by sharing hardware costs collectively, chip manufacturers can be more flexible, which means integrating more expertise within design tools like the software system equivalent of a silicon compiler.


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