EW – Design Edition – DfR Design Analysis, Mentor FinFET Processes & More
Vincent Charbonneau posted on May 09, 2018 |

Cadence Automotive Verification IPs

Cadence Verification IPs. (Image courtesy of Cadence.)
Cadence Verification IPs. (Image courtesy of Cadence.)

Cadence has announced three Verification IP (VIP) systems: CoaXPress VIP for high-speed imaging, HyperRAM memory VIP and a VIP for the JEDEC Universal Flash Storage (UFS) 3.0 specification. All three systems allow early adopters of these standards to begin designing with the new specifications, ensuring compliance with the standard and achieving a path to IP and system-on-chip (SoC) verification closure.

The UFS 3.0 specification doubles the throughput bandwidth from 1333MB/s in UFS 2.1 to 2666MB/s in UFS3.0 to address the growing bandwidth, low power and responsiveness requirements of advanced automotive and mobile designs. The Memory Model for UFS 3.0 also provides full-stack functionality, including support for MIPI Unified Protocol 1.8 and MIPI M-PHYSM 4.1.

For more information, visit Cadence’s website.

DfR Design Analysis Software

Sherlock Automated Design Analysis software. (Image courtesy of DfR Solutions.)
Sherlock Automated Design Analysis software. (Image courtesy of DfR Solutions.)

DfR Solutions has launched the next release of Sherlock Automated Design Analysis software: Version 5.4. Features include Temperature-based finite element analysis (FEA), a Materials Library Expansion, Component Failure Modes, and a Sqlite Parts Library option. The Temperature-based FEA capability enables users to simulate boards experiencing simultaneous temperature-dependent mechanical and vibrational stresses, modeling to real-world conditions where devices are exposed to many stressors simultaneously. This analysis is performed directly inside of Sherlock software, without the need for other FEA tools.

In addition, version 5.4 includes 100 materials utilized in all sectors of the electronics industry: conformal coatings, potting materials, epoxy molding compounds and underfills. Temperature-dependent material effects are automatically incorporated, saving time in data entry and allowing designers and engineers to make reliability predictions faster and more efficiently.

Additional technical specifications are available on DfR’s website.

Imagination Integrated Development Environment

PVRStudio. (Image courtesy of Imagination Technologies.)
PVRStudio. (Image courtesy of Imagination Technologies.)

Imagination Technologies has introduced PVRStudio, an integrated development environment (IDE) that simplifies app and game development on embedded and mobile platforms. With PVRStudio 2018 Release 1, developers have access to a debugger for PowerVR GPUs, and can also debug programs that are executing on the CPU hardware while they are debugging programs on the GPU.

PVRStudio provides fine granularity debugging through direct access to programs running on the GPU’s unified shading core (USC), where most of the critical calculations for 3D graphics and compute applications are performed. The software’s concurrent debugging capability includes breakpoints, code stepping and memory layout of graphics shaders and compute kernels.

For more information, visit Imagination’s website.

Mentor FinFET Processes

Calibre nmPlatform. (Image courtesy of Mentor.)
Calibre nmPlatform. (Image courtesy of Mentor.)

Mentor has announced that several tools in its Calibre nmPlatform and Analog FastSPICE (AFS) Platform have been certified by TSMC for the latest versions of TSMC’s 5nm FinFET and 7nm FinFET Plus processes. The company also announced that it has updated its Calibre nmPlatform tools in support of TSMC’s Wafer-on-Waferchip stacking technology.

Enhancements to the Calibre nmPlatform include DRC and LVS sign off for dice with backside through-silicon vias, interface alignment, and connectivity checks for die-to-die as well as die-to-package stacking. Further improvements include parasitic extraction on backside routing layers, interposers with through-silicon vias and interface coupling.

A detailed breakdown of Calibre’s features can be found on Mentor’s website.

Renesas Synergy Website for IoT Developers

Renesas Synergy Gallery. (Image courtesy of Renesas.)
Renesas Synergy Gallery. (Image courtesy of Renesas.)

Renesas has launched its updated Synergy Platform website and Solutions Gallery. The site refresh makes it easier for Renesas Synergy users to take advantage of the entire Synergy ecosystem, including LTE cellular, Bluetooth Low Energy, Wi-Fi connectivity and security measures. In addition, users now have streamlined access to applications such as connectivity to enterprise cloud services, human machine interface and industrial communication protocols.

“The Synergy Platform has grown tremendously since its introduction—through both content from Renesas and contributions from our many trusted hardware and software partners,” said Peter Carbone, vice president, Synergy Platform Business Division, Renesas. “Our new website and Solutions Gallery puts all the required building blocks for embedded IoT design right at our users’ fingertips, and we can’t wait to see what new innovations they will create next.”

For more information, visit Renesas’ website.

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