EW – Design Edition – Cadence Verification Suite, Synopsys Software Integrity Platform & More
Vincent Charbonneau posted on September 06, 2017 | | 2501 views

Altium Announces Annual PCB Design Summit

Altium has announced its first annual PCB design software conference created to help engineers grow their design expertise and contribute to the advancement of the electronics design community. “AltiumLive 2017: Annual PCB Design Summit” will grant attendees the opportunity to learn new skills, interact with like-minded engineers and get inspired to design next-generation electronics from industry icons and design masters.

“We’re thrilled to be hosting some of the world’s top PCB design professionals at this unique event,” said Ted Pawela, Chief Marketing Officer at Altium. “With our agenda of expert speakers, professional development courses, product updates and even a charity design challenge benefiting STEM education, AltiumLive 2017 will provide designers an amazing opportunity to learn from, be inspired by and contribute to the PCB design community.”

The summit will take place in San Diego on October 3rd and 4th. For more information, visit Altium’s website.

Cadence Optimizes its Verification Suite

Cadence has announced that its full-flow digital and signoff tools and the Cadence Verification Suite have been optimized to support Arm Cortex-A75 and Cortex-A55 CPUs, based on Arm DynamIQ technology and the Arm Mali-G72 GPU.

The Cadence RAKs accelerate physical implementation, signoff and verification of 7nm designs, allowing users to deliver mobile and consumer devices to market faster. With the delivery of the RAKs, Cadence is also providing technical support for Arm IP implementation. The digital and signoff tools have been configured to provide optimal power, performance and area (PPA) results using the RAKs, which include scripts, an example floorplan and documentation for Arm’s 7nm IP libraries.

For more information, visit Cadence’s website.

Mentor Upgrades its Functional Safety Program

Mentor Graphics has expanded its Mentor Safe functional safety program to include the Catapult High-Level Synthesis (HLS) platform and a host of analog/mixed-signal (AMS) IC verification products, including Eldo and the Analog FastSPICE (AFS) Platform.

The Catapult HLS Platform lets designers use industry-standard C++ and/or SystemC to describe an IC’s functional intent, enabling them to move up to a more productive abstraction level for both design and verification of ASICs and FPGAs. The platform is ideal for next-generation automotive IC designs, which are evolving rapidly due to increased demand for automotive vision, image processing, deep learning and other advanced functionalities.

For mixed-signal SoCs implemented in the nanometer CMOS technologies, the Analog FastSPICE Platform provides the required accuracy, performance and capacity. For automotive and other analog-centric ICs, Eldo offers a solution for safety and reliability verification as well as circuit analysis and diagnostics.

Additional information regarding Mentor’s Safe program can be found on the company’s website.

Synopsys Enhances Its Software Integrity Platform

Synopsys has released several updates to its Software Integrity Platform. In the era of digital transformation, building secure and reliable software is challenged by the rapid, complex and diverse nature of development cycles. The latest updates to the Synopsys Software Integrity Platform address these challenges with support for new programming languages, coverage for the Motor Industry Software Reliability Association (MISRA) guidelines and improved automation and integration capabilities.

Synopsys has also added a Defensics Fuzz Testing Software Development Kit (SDK) for building custom fuzz testing tools that detect critical security vulnerabilities in software applications and embedded devices. The SDK is built on the underlying technology of the Defensics Fuzz Testing tool, which was used to discover the infamous Heartbleed vulnerability. The Synopsys Fuzz Testing SDK is a framework that provides companies with the ability to test proprietary, niche or previously unsupported communication protocols and file formats.

For more information, visit Synopsys’ website.

Zuken Releases Version 18 of CADSTAR

Zuken has released CADSTAR 18, which includes better support for communication between multidisciplinary design teams through the CADSTAR Redlining markup tool. This version of the CADSTAR desktop PCB design software also supports industry requirements for high-speed design and includes performance enhancements and ease-of-use features. The Activ-45 router has also been updated, making the routing experience more intuitive and giving users more control over their designs.

Support for high-speed design is achieved through improved accuracy in capacitance calculations for SI Verify. In turn, simulating vias more accurately ensures that board behavior closely meets design expectations, increasing design quality.

A full list of CADSTAR 18’s features is located on Zuken’s website.

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