Stanford Engineers Exhibit a Prototype for a Computer-on-a-Chip
Goran Radanovic posted on March 01, 2019 |

Laptops and mini pads have proven that computers are shrinking, but a Stanford-led engineering team has expedited the process. Wanting to build a computer-on-a-chip, the team developed a prototype that unites memory and processing into one chip to make it more efficient and faster than passing data between separate chips, according to Boston Global Forum. The design of the chip had to contain processing circuits, power supply and memory storage to perform needed tasks, as well as be equipped with machine learning algorithms to make instant decisions. Wireless technology would enable the chip to send and receive data over the Internet. The design is known as the Internet of Everything, but to provide such functionality, the engineers had to design a new class of chips to serve as its foundation.

The engineering team displayed such a computer-on-a-chip on February 19 at the International Solid-State Circuits Conference held in San Francisco. The engineers did not compromise a computer’s functionality by developing the prototype, as they designed the chip to perform many advanced computing feats. Besides its size, the prototype’s other benefit is that its memory circuits and data processing use less than a tenth of the electricity as a comparable electronic device.

The engineers built the prototype using new data storage technology called resistive random access memory (RRAM), which contains features essential for the new class of chips. RRAM will enable the chip to retain data when it hibernates, pack more data into less space, and use energy more efficiently. The other key benefit of RRAM is that it allows engineers to build it on top of a processing circuit to integrate computation and data storage into one chip. While the French team at CEA-LETI grafted the RRAM onto a silicon processor, Stanford engineers improved the storage capacity of the RRAM by increasing the amount of information each storage unit could hold, as well as improving the endurance by developing an algorithm that prevents chip exhaustion. After testing the prototype, the engineers discovered that it should have a 10-year lifespan.

“This is what engineers do. We create a whole that is greater than the sum of its parts,” said Subhasish Mitra, a professor of electrical engineering and computer science who worked on the chip. Mitra also stated that the team’s electrical engineers and computer scientists integrated many hardware and software technologies on the prototype, which has a diameter the size of a pencil eraser. The Stanford-led team was thrilled that chip manufacturers have shown interest in the prototype. Mitra stated that the experience the team gained from the development of the prototype had spurred them to make the next generation faster, smaller, cheaper and more capable, according to Stanford News.

For further reading on chip manufacturing, check out New Manufacturing Technique for Ultra-Low-Power Computer Chips.

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