Verify FPGA and ASIC Video Streaming Capabilities on MATLAB or Simulink
Shawn Wasserman posted on May 20, 2015 |
VHDL and Verilog code synthesized from Vision HDL Toolbox and HDL Coder.

VHDL and Verilog code synthesized from Vision HDL Toolbox and HDL Coder.

MathWorks
has released the Vision HDL Toolbox, a library of image processing and computer vision algorithms designed for field-programmable gate arrays (FPGA) and application-specific integrated circuit (ASIC).

The Vision HDL Toolbox is designed to support engineers implementing FPGA and ASIC for automatic conversion of frame sizes, frame rates, interface types and frame-to-pixel. The reader can also be coupled with the HDL Coder to generate bender-independent HDL code.

Additionally, the HDL Verifier can connect the code to frame-based testing modules which can run in MATLAB or Simulink.

With this link to MATLAB and Simulink, users will be able to verify and simulate their designs before they go to market. Additionally, users will be able to combine their vision-based code with the remaining control code produced on Simulink or MATLAB. This will help to close the loop and allow for a more complete design, verification and simulation of the entire control system.

“FPGAs in particular are an increasingly popular platform for image processing and computer vision systems,” said John Zhao, marketing manager at MathWorks. “The new Vision HDL Toolbox has been created to help developers prototype and implement systems faster, with shortened design cycles, and more efficiently, through the ability to identify design errors early in the workflow and minimize the time needed for writing HDL code.”

The Vision HDL Toolbox is available on the 2015a release of MATLAB and Simulink. Other features include:

  • Image enhancements, filtering and statistics
  • Frame-based processing capabilities in MATLAB and Simulink
  • Video sync
  • 60FPS and 1080p video and other configurations

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