Epiphany Multi-core Concept


Image CourtestyAdapteva

Adapteva turned up in the news recently, here and here, coinciding with the introduction of their Epiphany-IV 64-core chip and an OpenCL compiler.

It was almost two years ago now that I, and probably many others, was introduced to Adapteva via this EETimes article. It was a fascinating look at the inspirational efforts that brought an integrated circuit to life. It was also an introduction to a technology designed to deliver a low-power, computationally powerful processor. At its heart is an array of processing nodes, see below, each containing a 32-bit floating-point processor, local memory (SRAM),a router and a Direct Memory Access (DMA) engine. With their new 64-core chip Adapteva claims performance of 50 Gflops/watt.

When looking at a low power anything it seems almost inevitable that you wind up at wireless. If that anything is a powerful compute engine one starts thinking about the power needed for image processing in today’s smartphones. Not surprising wireless devices are in focus of material on the website (www.adapteva.com). Further, the engine is offered as an IP core to be added to other processors. We have long speculated that Apple is implementing HW accelerators in their A(x) processors. It will be interesting to see how, and by whom, Adapteva’s technology is used. Certainly the release of an OpenCL kit should help in this process. To pull a quote from the HPCwire article:

"Everybody is very impressed by the numbers," Olofsson told HPCwire. "They just haven't quite been convinced they can program this thing."

 

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