Hybrid Memory Cube Interface Specification Released
Don Scansen posted on August 22, 2012 | 5452 views
Hybrid Memory CubeHybrid Memory Cube
There's no doubt that 3D technology is heating up - especially in the news. In the field of microelectronics, there are several approaches often leading to debate on just exactly what constitutes a 3D integrated circuit.

Intel currently manufactures a 3D transistor referred to as Tri-Gate that takes conventional CMOS beyond planar channel technology that was the mainstay for decades. There were even earlier examples of vertical channels when the horizontal dimension was insufficient going back to Samsung's release of the first DRAM with recessed channel array transistors (RCAT).

There have also been somewhat confusing announcements of 3D integrated circuits or 3DIC as a collection of individual chips stacked or placed together on a single package substrate. IN one instance, my colleague Paul Boldt examined these somewhat liberal public relations descriptions in a two part analysis of the latest Xilinx FPGA (Part 2 is available here). The Xilinx press release played with the definition of 3D in what was really a question of 2.5D. Practitioners and the better prepared analysts reserve the 3DIC moniker for active integrated circuit substrates stacked with interconnection provided by through silicon vias (TSV) placed vertically within working circuits.

But a true 3DIC using the definition above can be applied to the Hybrid Memory Cube or HMC. The devices are not yet in production, but the consortium including heavyweight memory makers Micron and Samsung started laying the groundwork for the technology a few years ago. A big part of ensuring the success of new technologies like HMC - revolutionary in the consortium's words - is to allow sufficient time to get several players working together and building consensus through formal or de facto standards.

Last week, the Hybrid Memory Cube Consortium announced its first draft of the technology's interface specification.

This first draft specification is targeted to high performance networking and industrial applications and calls upon consortium members to refine the current short-reach interconnection revision to allow ultra short-reach physical layer memory support for FPGA, ASIC and ASSP chips.

Going back to the idea of consensus and standards, this is an important milestone for the eventual adoption of the technology. There is not consensus on when the HMC or any other 3D memory will see the production floor, but the market and performance drivers for finally taking a step up are certainly starting to align.

You can read the complete press release after the break or at
http://hybridmemorycube.org/files/20120813_HMC_DSRelease.pdf.


 

First Draft of Hybrid Memory Cube Interface Specification Released 

 

Industry Leaders on Track to Complete Final Specification by Year End 

 

BOISE, Idaho and San Jose, CA, August 14, 2012 – The Hybrid Memory Cube Consortium 

(HMCC), led by Micron Technology, Inc., and Samsung Electronics Co., Ltd., today announced that 

its developer members have released the initial draft of the Hybrid Memory Cube (HMC) interface 

specification to a rapidly growing number of industry adopters.  Issuance of the draft puts the 

consortium on schedule to release the final version by the end of this year. The industry 

specification will enable adopters to fully develop designs that leverage HMC’s innovative 

technology, which has the potential to boost performance in a wide range of applications.  

 

The initial specification draft consists of an interface protocol and short-reach interconnection 

across physical layers (PHYs) targeted for high-performance networking, industrial, and test and 

measurement applications. The next step in development of the specification calls for the 

consortium’s adopters and developers to refine the specification and define an ultra short-reach 

PHY for applications requiring tightly coupled or close proximity memory support for FPGAs, 

ASICs and ASSPs.    

“With the draft standard now available for final input and modification by adopter members, we’re 

excited to move one step closer to enabling the Hybrid Memory Cube and the latest generation of 

28-nanometer (nm) FPGAs to be easily integrated into high-performance systems,”  said Rob 

Sturgill, architect, at Altera. “The steady progress among the consortium’s member companies for 

defining a new standard bodes well for businesses who would like to achieve unprecedented system 

performance and bandwidth by incorporating the Hybrid Memory Cube into their product 

strategies.”  

 

The interface specification reflects a focused collaboration among several of the world’s leading 

technology providers. Micron and Samsung, the initial developing members of the HMCC, are 

working closely with Altera Corporation, ARM, HP, IBM, Microsoft Corporation, Open-Silicon, 

Inc., SK hynix Co., and Xilinx, Inc., to allow HMC to pave the way for a wide range of advances in 

electronics. 

  

“As system designers face the simultaneous challenges of meeting exploding bandwidth 

requirements while staying within their power budgets, Xilinx is committed to technologies that 

allow them to address the bottlenecks in their systems while maintaining an acceptable level of 

power consumption,” said Hugh Durdan, Vice President, Portfolio & Solutions Marketing at Xilinx. 

“The progress that’s been made on the HMC specification is extremely exciting to Xilinx because of 

the increasingly important role that our 28nm high-performance, low-power FPGAs is playing in 

high-performance systems.” 

  

As envisioned, HMC capabilities will leap beyond current and near-term memory architectures in 

the areas of performance, packaging and power efficiencies, offering a major shift from present 

memory technology.  

 

One of the primary challenges facing the industry -- and a key motivation for forming the HMCC -- 

is that the memory bandwidth required by high-performance computers and next-generation 

networking equipment has increased beyond what conventional memory architectures can efficiently 

provide. 

 

The term “memory wall” has been used to describe this challenge. Breaking through the memory 

wall requires an architecture such as HMC that can provide increased density and bandwidth with 

significantly lower power consumption. 

 

Adopter membership in the HMCC is available to any company interested in participating in 

development of the specification. The HMCC already has responded to interest from 

more than 115 prospective adopters.  The final interface specification is scheduled for completion 

and release by the end of 2012. 

 

Additional information, technical support specifications and other tools for adopting the technology 

can be found at www.hybridmemorycube.org. 

 

About the HMCC 

Founded by leading members of the world’s semiconductor community, the Hybrid Memory Cube 

Consortium (HMCC) is dedicated to the development and establishment of an industry-standard 

interface specification for the Hybrid Memory Cube technology. Members of the consortium 

include Altera Corporation, ARM, HP, IBM, Micron Technology, Microsoft Corporation,  Open- 

Silicon, Inc., Samsung Electronics Co., Ltd.,  SK hynix Co., and Xilinx, Inc.  More than 115 

prospective adopters are exploring consortium membership. To learn more about the HMCC, visit 

www.hybridmemorycube.org. 

 

# # # 

 

Contacts: Scott Stevens   John Lucas 

  Micron Technology, Inc. Samsung Electronics Co., Ltd. 

  +1.512.288.4050  +1.408.544.4363 

sstevens@micron.com  j.lucas@ssi.samsung.com 

 

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