posted on July 19, 2012 |
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Maybe it was Avatar, maybe not, but for whatever reason 3D is hot. There was plenty of chatter with a 3D spin around Intel’s tri-gate announcement
last year. More recently a Barron’s headline read “Xilinx: 3-D Chip a Route to More Complex Semiconductors
”. It was certainly an upbeat article, almost giddy with phraseology including “it’s huge”. Why all the excitement? Is it because of the arrangement of multiple die within a single package? From the Barron’s article “... with the 3-D part deriving from the fact that two chips are “stacked” inside the package...”. It was not however readily apparent what the actual advance is was. Certainly Barron’s appears to focus on a 3D stacking of dice, but multi-chip packages are well known. In the end two questions: to what does the 3D term refer and what is the actual advance here? Let’s poke around a bit with a search, and then dig into Xilinx’s original press release, and the USPTO database.
Slide courtesy Freescale Marketing
An EETimes article
from March 2011 popped up very quickly in initial searching. The article, which was a reprint of a Xilinx publication, very clearly discusses the placement of die side-by-side on a silicon interposer. This is also illustrated in a package cross-section presented in Figure 3. In this cross-section, reproduced here, the two active die are seen at the top of the image. The die edges are at the very left of the image. So, we know the active die are not stacked. In fact the article specifically teaches away from stacking the die:
“By positioning dice next to each other and interfaced to the ball-grid array, the device avoids the thermal flux, signal integrity and design tool flow issues that would have accompanied a purely vertical die-stacking approach.”
So, from where did this 3D talk originate? The Xilinx press release announcing initial shipments
was titled “Xilinx ships World’s First Heterogeneous 3D FPGA." We know the active dice are not stacked, so maybe the 3D reference actually includes the silicon interposer to which the active die are connected. Maybe a bit of a red herring, but it does come back to the notion of perpetual motion. The second time around and the interpretation moves away from the original, even with an interview.
Now to the question of the actual development. The side-by-side arrangement of multiple die in a package is not new. Freescale, for example, implements a similar orientation in their Redistributed Chip Packaging (RCP) technology
The Xilinx press release said “world’s first heterogeneous 3D FPGA”. The first sentence then adds the phrase “all programmable”. So on a macro scale the development may simply be the implementation of this packaging technology to the heterogeous combination of die that includes an FPGA.
What about a finer scale? Is there a Xilinx technology within this genre of packaging that makes their “heterogeneous 3D FPGA” possible? Off to the US patent office database. Searching the published applications finds a number of recent documents in the area of the packaging. It may be within these documents that specific aspects of technology that allow the integration of an FPGA and transceivers in a single package are described. They might include advances that improve noise isolation or heat dissipation, for example. There is also the possibility that patent applications related to the enabling bits of technology are not yet be published. Whatever the case, it would not surprise if the real excitement lies in a more subtle aspect of the technology. However, to find out we have to get off the perpetual motion machine and look around.