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What is the difference between a Verilog task and a Verilog function in Electrical Eng? View All

8 years ago - 9 months left to answer. - 2 responses - Report Abuse
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Homer simpson
A function shall execute in one simulation time unit;
a task can contain time-controlling statements.

A function cannot enable a task;
a task can enable other tasks or functions.

A function shall have at least one input type argument
and shall not have an output or inout type argument;
a task can have zero or more arguments of any type.

A function shall return a single value;
a task shall not return a value.

8 years ago


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shilpi goenka
Verilog is a hardware description language, meaning that various
blocks of code directly map into hardware. Therefore, the designers must always have in mind the circuit they want to implement, not the program they want to write.

Task and function enhancements. SystemVerilog adds several enhancements to the Verilog task and function constructs. Only a few of the enhancements are highlighted in this article.

* Function return values can have a "void" return type. Void functions can be called the same as a Verilog task. The difference between a void function and a task is that Verilog functions have several semantic restrictions, such as no time controls.
* Functions can have any number of inputs, outputs and inouts, including none.
* Values can be passed to a task or function in any order, using the task/function argument names. The syntax is the same as named module port connections.
* Task and function input arguments can be assigned a default value as part o

8 years ago


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